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Control Registers and Control Packets

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20.3.1.46 HBCA Interrupt Channel Offset Register (HBCAOFFSET)

Figure 20-64. HBCA Interrupt Channel Offset Register (HBCAOFFSET) [offset = 154h]

31 16

Reserved

R-0

15 8 7 6 5 0

Reserved sbz sbz HBCA

R-0 R-0 R-0 R-0

LEGEND: R = Read only; -n = value after reset

Table 20-52. HBCA Interrupt Channel Offset Register (HBCAOFFSET) Field Descriptions

Bit Field Value Description

31-16 Reserved 0 Read returns 0. Writes have no effect.

7-6 sbz 0 These bits should always be programmed as zero.

5-0 HBCA Channel causing HBC interrupt Group A. These bits contain the channel number of the pending

interrupt for Group A if the corresponding interrupt enable is set.

Note: Reading this location clears the corresponding interrupt pending flag (see

Section 20.3.1.41) with the highest priority.

0 No interrupt is pending.

1h Channel 0 is causing the pending interrupt Group A.

: :

20h Channel 31 is causing the pending interrupt Group A.

20.3.1.47 BTCA Interrupt Channel Offset Register (BTCAOFFSET)

Figure 20-65. BTCA Interrupt Channel Offset Register (BTCAOFFSET) [offset = 158h]

31 16

Reserved

R-0

15 8 7 6 5 0

Reserved sbz sbz BTCA

R-0 R-0 R-0 R-0

LEGEND: R = Read only; -n = value after reset

Table 20-53. BTCA Interrupt Channel Offset Register (BTCAOFFSET) Field Descriptions

Bit Field Value Description

31-16 Reserved 0 Read returns 0. Writes have no effect.

7-6 sbz 0 These bits should always be programmed as zero.

5-0 BTCA Channel causing BTC interrupt Group A. These bits contain the channel number of the pending

interrupt for Group A if the corresponding interrupt enable is set.

Note: Reading this location clears the corresponding interrupt pending flag (see

Section 20.3.1.42) with the highest priority.

0 No interrupt is pending.

1h Channel 0 is causing the pending interrupt Group A.

: :

20h Channel 31 is causing the pending interrupt Group A.

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Direct Memory Access Controller (DMA) Module SPNU562–May 2014

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