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20.3.1.42 BTC Interrupt Flag Register (BTCFLAG)
Figure 20-60. BTC Interrupt Flag Register (BTCFLAG) [offset = 13Ch]
31 0
BTCI[31:0]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 20-48. BTC Interrupt Flag Register (BTCFLAG) Field Descriptions
Bit Field Value Description
31-0 BTCI[n] Block transfer complete (BTC) flags. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1,
and so on.
Note: Reading from the respective interrupt channel offset register also clears the
corresponding flag (see Section 20.3.1.47 and Section 20.3.1.52).
Note: The state of the flag bit can be polled even if the corresponding interrupt enable bit is
cleared.
0 Read: BTC interrupt of the corresponding channel is not pending.
Write: No effect.
1 Read: BTC interrupt of the corresponding channel is pending.
Write: The flag is cleared.
20.3.1.43 BER Interrupt Flag Register (BERFLAG)
Figure 20-61. BER Interrupt Flag Register (BERFLAG) [offset = 144h]
31 0
BERI[31:0]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 20-49. BER Interrupt Flag Register (BERFLAG) Field Descriptions
Bit Field Value Description
31-0 BERI[n] Bus error (BER) flags. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and so on.
Note: Reading from the respective interrupt channel offset register also clears the
corresponding flag (see Section 20.3.1.48 and Section 20.3.1.53).
Note: The state of the flag bit can be polled even if the corresponding interrupt enable bit is
cleared.
0 Read: BER interrupt of the corresponding channel is not pending.
Write: No effect.
1 Read: BER interrupt of the corresponding channel is pending.
Write: The flag is cleared.
730
Direct Memory Access Controller (DMA) Module SPNU562–May 2014
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