Datasheet

Control Registers and Control Packets

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20.3.1.38 Global Interrupt Flag Register (GINTFLAG)

Figure 20-56. Global Interrupt Flag Register (GINTFLAG) [offset = 11Ch]

31 0

GINT[31:0]

R/WP-0

LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset

Table 20-44. Global Interrupt Flag Register (GINTFLAG) Field Descriptions

Bit Field Value Description

31-0 GINT[n] Global interrupt flags. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and so on. A

global interrupt flag bit is an OR function of FTC, LFS, HBC, BTC and BER interrupt flags.

0 No interrupt is pending on the corresponding channel.

1 One or more of the five interrupt types (FTC, LFS, HBC, BTC, or BER) is pending on the corresponding

channel.

20.3.1.39 FTC Interrupt Flag Register (FTCFLAG)

Figure 20-57. FTC Interrupt Flag Register (FTCFLAG) [offset = 124h]

31 0

FTCI[31:0]

R/WP-0

LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset

Table 20-45. FTC INTERRUPT FLAG Register (FTCFLAG) Field Descriptions

Bit Field Value Description

31-0 FTCI[n] Frame transfer complete (FTC) flags. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1,

and so on.

Note: Reading from the respective interrupt channel offset register also clears the

corresponding flag (see Section 20.3.1.44 and Section 20.3.1.49).

Note: The state of the flag bit can be polled even if the corresponding interrupt enable bit is

cleared.

0 Read: FTC interrupt of the corresponding channel is not pending.

Write: No effect.

1 Read: FTC interrupt of the corresponding channel is pending.

Write: The flag is cleared.

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Direct Memory Access Controller (DMA) Module SPNU562–May 2014

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