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Control Registers and Control Packets

20.3.1.32 LFS Interrupt Enable Set Register (LFSINTENAS)

Figure 20-50. LFS Interrupt Enable Set Register (LFSINTENAS) [offset = ECh]

31 0

LFSINTENA[31:0]

R/WP-0

LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset

Table 20-38. LFS Interrupt Enable Set Register (LFSINTENAS) Field Descriptions

Bit Field Value Description

31-0 LFSINTENA[n] Last frame started (LFS) interrupt enable. Bit 0 corresponds to channel 0, bit 1 corresponds to

channel 1, and so on.

0 Read: Corresponding LFS interrupt of a channel is disabled.

Write: No effect.

1 Read and write: LFS interrupt of the corresponding channel is disabled.

20.3.1.33 LFS Interrupt Enable Reset Register (LFSINTENAR)

Figure 20-51. LFS Interrupt Enable Reset Register (LFSINTENAR) [offset = F4h]

31 0

LFSINTDIS[31:0]

R/WP-0

LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset

Table 20-39. LFS Interrupt Enable Reset Register (LFSINTENAR) Field Descriptions

Bit Field Value Description

31-0 LFSINTDIS[n] Last frame started (LFS) interrupt disable. Bit 0 corresponds to channel 0, bit 1 corresponds to

channel 1, and so on.

0 Read: LFS interrupt of the corresponding channel is disabled.

Write: No effect.

1 Read: LFS interrupt of the corresponding channel is enabled.

Write: LFS interrupt of the corresponding channel is disabled.

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SPNU562–May 2014 Direct Memory Access Controller (DMA) Module

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