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Control Registers and Control Packets

20.3.1.28 BTC Interrupt Mapping Register (BTCMAP)

Figure 20-46. BTC Interrupt Mapping Register (BTCMAP) [offset = CCh]

31 0

BTCAB[31:0]

R/WP-0

LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset

Table 20-34. BTC Interrupt Mapping Register (BTCMAP) Field Descriptions

Bit Field Value Description

31-0 BTCAB[n] Block transfer complete (BTC) interrupt to Group A or Group B. Bit 0 corresponds to channel 0, bit 1

corresponds to channel 1, and so on.

0 BTC interrupt of the corresponding channel is routed to Group A.

1 BTC interrupt of the corresponding channel is routed to Group B.

20.3.1.29 BER Interrupt Mapping Register (BERMAP)

NOTE: On this device, Group B Interrupts are not implemented; therefore, user software should

configure only Group A interrupts.

Figure 20-47. BER Interrupt Mapping Register (BERMAP) [offset = D4h]

31 0

BERAB[31:0]

R/WP-0

LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset

Table 20-35. BER Interrupt Mapping Register (BERMAP) Field Descriptions

Bit Field Value Description

31-0 BERAB[n] Bus error (BER) interrupt to Group A or Group B. Bit 0 corresponds to channel 0, bit 1 corresponds to

channel 1, and so on.

0 BER interrupt of the corresponding channel is routed to Group A.

1 BER interrupt of the corresponding channel is routed to Group B.

723

SPNU562–May 2014 Direct Memory Access Controller (DMA) Module

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