Datasheet

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Control Registers and Control Packets
20.3.1.24 Port Assignment Register 3 (PAR3)
Figure 20-42. Port Assignment Register 3 (PAR3) [offset = a0h]
31 30 28 27 26 24 23 22 20 19 18 16
Rsvd CH24PA Rsvd CH25PA Rsvd CH26PA Rsvd CH27PA
R-0 R/WP-0 R-0 R/WP-0 R-0 R/WP-0 R-0 R/WP-0
15 14 12 11 10 8 7 6 4 3 2 0
Rsvd CH28PA Rsvd CH29PA Rsvd CH30PA Rsvd CH31PA
R-0 R/WP-0 R-0 R/WP-0 R-0 R/WP-0 R-0 R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 20-30. Port Assignment Register 3 (PAR3) Field Descriptions
Bit Field Value Description
31 Reserved 0 Read returns 0. Writes have no effect.
30-28 CH24PA These bit fields determine to which port channel 24 is assigned.
1h Port A and B combined, A read/B write
2h Port A only
3h Port B only
Others Port A and B combined, B read/A write
27 Reserved 0 Read returns 0. Writes have no effect.
26-24 CH25PA These bit fields determine to which port channel 25 is assigned. Refer CH24PA for description.
23 Reserved 0 Read returns 0. Writes have no effect.
22-20 CH26PA These bit fields determine to which port channel 26 is assigned. Refer CH24PA for description.
19 Reserved 0 Read returns 0. Writes have no effect.
18-16 CH27PA These bit fields determine to which port channel 27 is assigned. Refer CH24PA for description.
15 Reserved 0 Read returns 0. Writes have no effect.
14-12 CH28PA These bit fields determine to which port channel 28 is assigned. Refer CH24PA for description.
11 Reserved 0 Read returns 0. Writes have no effect.
10-8 CH29PA These bit fields determine to which port channel 29 is assigned. Refer CH24PA for description.
7 Reserved 0 Read returns 0. Writes have no effect.
6-4 CH30PA These bit fields determine to which port channel 30 is assigned. Refer CH24PA for description.
3 Reserved 0 Read returns 0. Writes have no effect.
2-0 CH31PA These bit fields determine to which port channel 31 is assigned. Refer CH24PA for description.
721
SPNU562May 2014 Direct Memory Access Controller (DMA) Module
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