Datasheet

Control Registers and Control Packets

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20.3.1.23 Port Assignment Register 2 (PAR2)

Figure 20-41. Port Assignment Register 2 (PAR2) [offset = 9Ch]

31 30 28 27 26 24 23 22 20 19 18 16

Rsvd CH0PA Rsvd CH1PA Rsvd CH2PA Rsvd CH3PA

R-0 R/WP-0 R-0 R/WP-0 R-0 R/WP-0 R-0 R/WP-0

15 14 12 11 10 8 7 6 4 3 2 0

Rsvd CH4PA Rsvd CH5PA Rsvd CH6PA Rsvd CH7PA

R-0 R/WP-0 R-0 R/WP-0 R-0 R/WP-0 R-0 R/WP-0

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 20-29. Port Assignment Register 2 (PAR2) Field Descriptions

Bit Field Value Description

31 Reserved 0 Read returns 0. Writes have no effect.

30-28 CH16PA These bit fields determine to which port(s) channel 16 is assigned.

1h Port A and B combined, A read/B write

2h Port A only

3h Port B only

Others Port A and B combined, B read/A write

27 Reserved 0 Read returns 0. Writes have no effect.

26-24 CH17PA These bit fields determine to which port channel 17 is assigned. Refer CH16PA for description.

23 Reserved 0 Read returns 0. Writes have no effect.

22-20 CH18PA These bit fields determine to which port channel 18 is assigned. Refer CH16PA for description.

19 Reserved 0 Read returns 0. Writes have no effect.

18-16 CH19PA These bit fields determine to which port channel 19 is assigned. Refer CH16PA for description.

15 Reserved 0 Read returns 0. Writes have no effect.

14-12 CH20PA These bit fields determine to which port channel 20 is assigned. Refer CH16PA for description.

11 Reserved 0 Read returns 0. Writes have no effect.

10-8 CH21PA These bit fields determine to which port channel 21 is assigned. Refer CH16PA for description.

7 Reserved 0 Read returns 0. Writes have no effect.

6-4 CH22PA These bit fields determine to which port channel 22 is assigned. Refer CH16PA for description.

3 Reserved 0 Read returns 0. Writes have no effect.

2-0 CH23PA These bit fields determine to which port channel 23 is assigned. Refer CH16PA for description.

720

Direct Memory Access Controller (DMA) Module SPNU562–May 2014

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