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Control Registers and Control Packets

20.3.1.22 Port Assignment Register 1 (PAR1)

Figure 20-40. Port Assignment Register 1 (PAR1) [offset = 98h]

31 30 28 27 26 24 23 22 20 19 18 16

Rsvd CH8PA Rsvd CH9PA Rsvd CH10PA Rsvd CH11PA

R-0 R/WP-0 R-0 R/WP-0 R-0 R/WP-0 R-0 R/WP-0

15 14 12 11 10 8 7 6 4 3 2 0

Rsvd CH12PA Rsvd CH13PA Rsvd CH14PA Rsvd CH15PA

R-0 R/WP-0 R-0 R/WP-0 R-0 R/WP-0 R-0 R/WP-0

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 20-28. Port Assignment Register 1 (PAR1) Field Descriptions

Bit Field Value Description

31 Reserved 0 Read returns 0. Writes have no effect.

30-28 CH8PA These bit fields determine to which port channel 8 is assigned.

1h Port A and B combined, A read/B write

2h Port A only

3h Port B only

Others Port A and B combined, B read/A write

27 Reserved 0 Read returns 0. Writes have no effect.

26-24 CH9PA These bit fields determine to which port channel 9 is assigned. Refer CH8PA for description.

23 Reserved 0 Read returns 0. Writes have no effect.

22-20 CH10PA These bit fields determine to which port channel 10 is assigned. Refer CH8PA for description.

19 Reserved 0 Read returns 0. Writes have no effect.

18-16 CH11PA These bit fields determine to which port channel 11 is assigned. Refer CH8PA for description.

15 Reserved 0 Read returns 0. Writes have no effect.

14-12 CH12PA These bit fields determine to which port channel 12 is assigned. Refer CH8PA for description.

11 Reserved 0 Read returns 0. Writes have no effect.

10-8 CH13PA These bit fields determine to which port channel 13 is assigned. Refer CH8PA for description.

7 Reserved 0 Read returns 0. Writes have no effect.

6-4 CH14PA These bit fields determine to which port channel 14 is assigned. Refer CH8PA for description.

3 Reserved 0 Read returns 0. Writes have no effect.

2-0 CH15PA These bit fields determine to which port channel 15 is assigned. Refer CH8PA for description.

719

SPNU562–May 2014 Direct Memory Access Controller (DMA) Module

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