Datasheet

Control Registers and Control Packets

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20.3.1.17 DMA Request Assignment Register 4 (DREQASI4)

Figure 20-35. DMA Request Assignment Register 4 (DREQASI4) [offset = 64h]

31 30 29 24 23 22 21 16

Reserved CH16ASI Reserved CH17ASI

R-0 R/WP-10h R-0 R/WP-11h

15 14 13 8 7 6 5 0

Reserved CH18ASI Reserved CH19ASI

R-0 R/WP-12h R-0 R/WP-13h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 20-23. DMA Request Assignment Register 4 (DREQASI4) Field Descriptions

Bit Field Value Description

31-30 Reserved 0 Read returns 0. Writes have no effect.

29-24 CH16ASI Channel 16 assignment. This bit field chooses the DMA request assignment for channel 16.

0 DMA request line 0 triggers channel 16.

: :

1Fh DMA request line 31 triggers channel 16.

23-22 Reserved 0 Read returns 0. Writes have no effect.

21-16 CH17ASI Channel 17 assignment. This bit field chooses the DMA request assignment for channel 17.

0 DMA request line 0 triggers channel 17.

: :

1Fh DMA request line 31 triggers channel 17.

15-14 Reserved 0 Read returns 0. Writes have no effect.

13-8 CH18ASI Channel 18 assignment. This bit field chooses the DMA request assignment for channel 18.

0 DMA request line 0 triggers channel 18.

: :

1Fh DMA request line 31 triggers channel 18.

7-6 Reserved 0 Read returns 0. Writes have no effect.

5-0 CH19ASI Channel 3 assignment. This bit field chooses the DMA request assignment for channel 19.

0 DMA request line 0 triggers channel 19.

: :

1Fh DMA request line 31 triggers channel 19.

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Direct Memory Access Controller (DMA) Module SPNU562–May 2014

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