Datasheet

Control Registers and Control Packets

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20.3.1.15 DMA Request Assignment Register 2 (DREQASI2)

Figure 20-33. DMA Request Assignment Register 2 (DREQASI2) [offset = 5Ch]

31 30 29 24 23 22 21 16

Reserved CH8ASI Reserved CH9ASI

R-0 R/WP-8h R-0 R/WP-9h

15 14 13 8 7 6 5 0

Reserved CH10ASI Reserved CH11ASI

R-0 R/WP-Ah R-0 R/WP-Bh

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 20-21. DMA Request Assignment Register 2 (DREQASI2) Field Descriptions

Bit Field Value Description

31-30 Reserved 0 Read returns 0. Writes have no effect.

29-24 CH8ASI Channel 8 assignment. This bit field chooses the DMA request assignment for channel 8.

0 DMA request line 0 triggers channel 8.

: :

1Fh DMA request line 31 triggers channel 8.

23-22 Reserved 0 Read returns 0. Writes have no effect.

21-16 CH9ASI Channel 9 assignment. This bit field chooses the DMA request assignment for channel 9.

0 DMA request line 0 triggers channel 9.

.: :

1Fh DMA request line 31 triggers channel 9.

15-14 Reserved 0 Read returns 0. Writes have no effect.

13-8 CH10ASI Channel 10 assignment. This bit field chooses the DMA request assignment for channel 10.

0 DMA request line 0 triggers channel 10.

: :

1Fh DMA request line 31 triggers channel 10.

7-6 Reserved 0 Read returns 0. Writes have no effect.

5-0 CH11ASI Channel 11 assignment. This bit field chooses the DMA request assignment for channel 11.

0 DMA request line 0 triggers channel 11.

: :

1Fh DMA request line 31 triggers channel 11.

712

Direct Memory Access Controller (DMA) Module SPNU562–May 2014

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