Datasheet

Control Registers and Control Packets

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20.3.1.13 DMA Request Assignment Register 0 (DREQASI0)

Figure 20-31. DMA Request Assignment Register 0 (DREQASI0) [offset = 54h]

31 30 29 24 23 22 21 16

Reserved CH0ASI Reserved CH1ASI

R-0 R/WP-0 R-0 R/WP-1h

15 14 13 8 7 6 5 0

Reserved CH2ASI Reserved CH3ASI

R-0 R/WP-2h R-0 R/WP-3h

LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset

Table 20-19. DMA Request Assignment Register 0 (DREQASI0) Field Descriptions

Bit Field Value Description

31-30 Reserved 0 Read returns 0. Writes have no effect.

29-24 CH0ASI Channel 0 assignment. This bit field chooses the DMA request assignment for channel 0.

0 DMA request line 0 triggers channel 0.

: :

1Fh DMA request line 31 triggers channel 0.

23-22 Reserved 0 Read returns 0. Writes have no effect.

21-16 CH1ASI Channel 1 assignment. This bit field chooses the DMA request assignment for channel 1.

0 DMA request line 0 triggers channel 1.

: :

1Fh DMA request line 31 triggers channel 1.

15-14 Reserved 0 Read returns 0. Writes have no effect.

13-8 CH2ASI Channel 2 assignment. This bit field chooses the DMA request assignment for channel 2.

0 DMA request line 0 triggers channel 2.

: :

1Fh DMA request line 31 triggers channel 2.

7-6 Reserved 0 Read returns 0. Writes have no effect.

5-0 CH3ASI Channel 3 assignment. This bit field chooses the DMA request assignment for channel 3.

0 DMA request line 0 triggers channel 3.

: :

1Fh DMA request line 31 triggers channel 3.

710

Direct Memory Access Controller (DMA) Module SPNU562–May 2014

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