Datasheet

Control Registers and Control Packets
www.ti.com
20.3.1.5 HW Channel Enable Set and Status Register (HWCHENAS)
Figure 20-23. HW Channel Enable Set and Status Register (HWCHENAS) [offset = 14h]
31 0
HWCHENA[31:0]
R-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 20-11. HW Channel Enable Set and Status Register (HWCHENAS) Field Descriptions
Bit Field Value Description
31-0 HWCHENA[n] Hardware channel enable bit. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and
so on. An active hardware DMA request cannot initiate a DMA transfer unless the corresponding
hardware enable bit is set.
The corresponding hardware enable bit is cleared automatically for the following conditions:
At the end of a block transfer if the auto-initiation bit AIM (see CHCTRL) is not active.
If a bus error is detected for an active channel.
Reading from HWCHENAS gives the status (enabled/disabled) of all channels.
0 The corresponding channel is disabled for hardware triggering.
1 The corresponding channel is enabled for hardware triggering.
20.3.1.6 HW Channel Enable Reset and Status Register (HWCHENAR)
Figure 20-24. HW Channel Enable Reset and Status Register (HWCHENAR) [offset = 1Ch]
31 0
HWCHDIS[31:0]
R-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 20-12. HW Channel Enable Reset and Status Register (HWCHENAR) Field Descriptions
Bit Field Value Description
31-0 HWCHDIS[n] HW channel disable bit. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and so on.
0 Read: The corresponding channel is disabled for HW triggering.
Write: No effect.
1 Read: The corresponding channel is enabled for HW triggering.
Write: The corresponding channel is disabled.
706
Direct Memory Access Controller (DMA) Module SPNU562May 2014
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated