Datasheet

Control Registers and Control Packets

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Table 20-5. DMA Control Registers (continued)

Offset Acronym Register Description Section

1F8h DMAMPR7S DMA Memory Protection Region 7 Start Address Register Section 20.3.1.85

1FCh DMAMPR7E DMA Memory Protection Region 7 End Address Register Section 20.3.1.86

228h DMASECCCTRL DMA Single bit ECC Control Register Section 20.3.1.87

230h DMAECCSBE DMA ECC Single bit Error Address Register Section 20.3.1.88

240h FIFOASTATREG FIFO A Status Register Section 20.3.1.89

244h FIFOBSTATREG FIFO B Status Register Section 20.3.1.90

330h DMAREQPS1 DMA Request Polarity Select Register 1 Section 20.3.1.91

334h DMAREQPS0 DMA Request Polarity Select Register 0 Section 20.3.1.92

340h TERECTRL TER Event Control Register Section 20.3.1.93

344h TERFLAG TER Event Flag Register Section 20.3.1.94

348h TERROFFSET TER Event Channel Offset Register Section 20.3.1.95

Table 20-6. Control Packet Memory Map

Offset Acronym Register Description Section

Primary Control Packet 0

00h ISADDR Initial Source Address Register Section 20.3.2.1

04h IDADDR Initial Destination Address Register Section 20.3.2.2

08h ITCOUNT Initial Transfer Count Register Section 20.3.2.3

10h CHCTRL Channel Control Register Section 20.3.2.4

14h EIOFF Element Index Offset Register Section 20.3.2.5

18h FIOFF Frame Index Offset Register Section 20.3.2.6

Working Control Packet 0

800h CSADDR Current Source Address Register Section 20.3.2.7

804h CDADDR Current Destination Address Register Section 20.3.2.8

808h CTCOUNT Current Transfer Count Register Section 20.3.2.9

702

Direct Memory Access Controller (DMA) Module SPNU562–May 2014

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