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20.2.17 ECC Testing
The ECC RAM is accessible to allow manually inserting faults so that the ECC checking feature can be
tested. Test mode is entered by asserting the TEST bit in the ECC Control Register (Section 20.3.1.65).
Once the bit is set, the ECC bits are mapped to the control packet RAM starting address A00h. The
sequence to test the ECC is:
1. Write the data location of the Control Packet RAM while keeping ECC_ENA active. The ECC bits will
get automatically written with the correct values in this step.
2. Enable ECC test mode by setting the TEST bit of the DMAPECR register.
3. To test single bit error correction capability, read back one of the data written earlier, flip one of the bits
and write it back. The same could be done for the ECC bits as well.
4. Similarly, to test double bit detection capability, read back one of the data written earlier, flip two bits
and write it back. The same could be done for the ECC bits as well.
5. Now read back the same data bits which was corrupted or for which the ECC was corrupted in the
earlier steps 3-4.
6. Depending on the kind of corruption created, for double bit error, read EDFLG and error address
captured in DMAPAR; similarly for single bit error, read SBERR in DMASECCCTRL and error address
in DMAECCSBE.
7. The check is successful if the flag and error address are updated successfully.
8. Clear the flags (EDFLG or SBERR as applicable) and read the error address.
9. To exit the test mode, initialize the data and ECC that were corrupted earlier, back to their original
values.
10. Finally, clear the TEST bit of the DMAPECR register.
NOTE: When in test mode, no ECC checking will be done when reading from ECC memory, but
ECC checking will be performed on the normal memory.
This offsets in Table 20-4 must be used to run the ECC diagnostics.
Table 20-4. ECC Mapping
Offset ECC of Control Packet (Only 9 bits are valid in the read)
A00h 0 (Lower 128 bits)
A04h 0 (Upper 128 bits)
A08h 1 (Lower 128 bits)
: :
AFCh 31 (Upper 128 bits)
20.2.18 Initializing RAM with ECC
After power up, the RAM content including the ECC bits cannot be guaranteed. To avoid ECC failures
when reading RAM, the RAM has to be initialized. The RAM can be initialized by writing known values into
it. When the known value is written, the corresponding ECC bit will be automatically calculated and
updated.
Another possibility to initialize the memory is to set a 4-bit key in the system module. This key triggers the
automatic initialization of all RAMs on the microcontroller. The RAM will be initialized to 0 and the ECC will
be initialized to their correct values.
To allow for ECC calculation during initialization, the ECC functionality has to be enabled as discussed in
Section 20.2.16.
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Direct Memory Access Controller (DMA) Module SPNU562–May 2014
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