Datasheet

CHANNEL
SPECIFIC
INTERRUPT
PARITY
ERROR
MPU
ERROR
ERROR
SIGNALING
MODULE
(ESM)
VECTOR
INTERRUPT
MODULE
(VIM)
CPU
FTCA
LFSA
HBCA
BTCA
PAR
MPU
High
Low
G
R
O
U
P
A
BERA
www.ti.com Module Operation
20.2.9 Interrupts
Each channel can be configured to generate interrupts on several transfer conditions:
• Frame transfer complete (FTC) interrupt: an interrupt is issued after the last element of a frame has
been transferred.
• Last frame transfer started (LFS) interrupt: an interrupt is issued before the first element of the last
frame of a block transfer has started.
• First half of block complete (HBC) interrupt: an interrupt is issued if more than half of the block is
transferred.
– If the number of frames n is odd, then the HBC interrupt is generated at the end of the frame when
(n+1) / 2 number of frames are left in the block.
– If the number of frames n is even, then the HBC interrupt is generated at the end of the frame after
n/2 number of frames are left in the block.
• Block transfer complete (BTC) interrupt: an interrupt is issued after the last element of the last frame
has been transferred.
• Bus error (BER) interrupt: an interrupt is issued when DMA detects an error on the bus. The BER
interrupt is connected to the ESM module.
• Memory Protection Unit error (MPU): an interrupt is issued when the DMA detects that the access falls
outside of a memory region programmed in the MPU registers of the DMA. The MPU interrupt is
connected to the ESM module.
• Parity error (PAR): an interrupt is issued when the DMA detects a parity error when reading one of the
control packets. The PAR interrupt is connected to the ESM module.
The DMA outputs 5 interrupt lines for control packet handling, a parity interrupt and a memory protection
interrupt (Figure 20-14). Each type of transfer interrupt condition is grouped together. For example, all
block-transfer complete interrupts that are routed to a port are combined (ORed). The channel that caused
the interrupt is given in the corresponding interrupt channel offset register. Priority between interrupts
among the same interrupt type is resolved by a fixed priority scheme. Priority between different interrupt
types is resolved in the Vector Interrupt Manager. Figure 20-15 explains the Frame Transfer Complete
Interrupt structure in detail.
NOTE: Each Channel Specific interrupts in DMA module are routed towards Group A or B to
support two different CPUs individually. For devices with Single CPU or Dual CPU where
both CPUs are running same code in delayed lock-step as safety feature:
Group A - Interrupts (FTC, LFS, HBC, BTC, and BER) are routed to the ARM CPU.
Group B - Interrupts (FTC, LFS, HBC, BTC, and BER) are not routed out.
User software should configure only Group A interrupts.
Figure 20-14. DMA Interrupts
691
SPNU562–May 2014 Direct Memory Access Controller (DMA) Module
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