Datasheet

Module Operation www.ti.com
20.2.7 DMA Request
There are three ways to start a DMA transfer:
• Software request: The transfer will be triggered by writing to SW Channel Enable Set and Status
Register (Section 20.3.1.7). The software request can trigger either a block or a frame transfer
depending on what the trigger type (TTYPE) bit is set to in the Channel Control Register
(Section 20.3.2.4).
• Hardware request: The DMA controller can handle up to 32 DMA Request lines. A hardware request
can trigger either a frame or a block transfer dependent on the setting of TTYPE control bit of the
Channel Control Register (Section 20.3.2.4).
• Triggered by other control packet: When a control packet finishes the programmed number of
transfers it can trigger another channel to initiate its transfers.
Each time a DMA request is made, either one frame transfer or one block transfer can be chosen. An
active DMA request signal will trigger a DMA transaction.
The DMA controller has a two-level buffer to capture HW requests per channel. When a HW request is
generated and the channel is enabled, the corresponding bit in the DMA Status Register
(Section 20.3.1.3) is set. The pending register acts as a first-level buffer. Typically, a peripheral acting as a
source of a transfer could initiate another request after its data registers have been read out by DMA,
even though that data has not been completely transferred to the destination. If a second HW request is
generated by the peripheral, the DMA controller has an extra request buffer to capture this second request
and service it after the first request is complete.
NOTE: The DMA cannot capture more than two requests at the same timee. Additional requests are
ignored until at least one pending request is completely processed. it.
The DMA controller also supports a mix of hardware and software requests on the same channel. Note
that such interchangeable usage may result into an out of sync for DMA channel and peripheral. The
application needs to be careful as the DMA does not have a built-in mechanism to protect against this loss
of synchronization.
If a software request is generated, the corresponding bit in the Channel Pending Register
(Section 20.3.1.2) is set accordingly. If the pending request is not completely serviced by the DMA and a
hardware request is generated by a peripheral onto the same channel, the DMA will capture and
recognize this hardware request into its request buffer.
NOTE: The DMA controller cannot recognize two software requests on the same channel if the first
software request is still pending. If such a request occurs, the DMA will discard it. Therefore,
the user S/W should check the pending register before issue a new software request.
20.2.8 Auto-Initiation
When Auto-initiation Mode (AIM) bit of Channel Control Register (Section 20.3.2.4) is enabled for a
channel and the channel is triggered by a software request for a block transfer, the channel will restart
again using the same channel information stored at the respective control packet after one block transfer
is completed. In the case of Hardware Request the channel needs to be retriggered each time after a
block is complete even if auto-initiation is enabled.
690
Direct Memory Access Controller (DMA) Module SPNU562–May 2014
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated