Datasheet

Frame Index Pointer
Base + 0x00
0x20
Initial Source Addr
Channel Configuration
Initial Destination Addr
Element Index Pointer
Initial Transfer Count
Frame Index Pointer
Initial Source Addr
Channel Configuration
Current Source Addr
Initial Destination Addr
Element Index Pointer
Current Destination Addr
Initial Transfer Count
Frame Index Pointer
Current Transfer Count
0x30
0x800
Current Source Addr
Current Source Addr
Reserved Reserved
Reserved
Current Destination Addr
Current Destination Addr
Current Transfer Count
Current Transfer Count
0x1F0
0x1E0
0x810
0x8F0
Base + 0xXXXC
Reserved
0x10
Primary CP0
Primary CP1
Primary CPnn
Working CP0
Working CP1
Working CPnn
Base + 0XXX0 Base + 0xXXX4 Base + 0xXXX8
Initial Scouce Addr
Channel Configuration
Initial Destination Addr Initial Transfer Count
Element Index Pointer
}
}
}
}
}
}
Y...
DMAREQ(0)
DMAREQ(1)
DMAREQ(2)
DMAREQ(63)
Ch 0
Control Packet 0
Y...
CH1ASI[5:0]
DMAREQ(0)
DMAREQ(1)
DMAREQ(2)
DMAREQ(63)
CH0ASI[5:0]
Control Packet 1
YY.
Control Packet 31
Ch 1
Y...
CH31ASI[5:0]
DMAREQ(0)
DMAREQ(1)
DMAREQ(2)
DMAREQ(63)
Ch 31
Y...
Module Operation www.ti.com
Figure 20-4. DMA Request Mapping and Control Packet Organization
Figure 20-5. Control Packet Organization and Memory Map
682
Direct Memory Access Controller (DMA) Module SPNU562–May 2014
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