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Module Operation

respective channels in the PARx registers.

20.2 Module Operation

The DMA acts as an independent master in the platform architecture. DMA will attempt to execute up to

two channels at the same time to maximize system throughput. Each channel can be configured to utilize

either Port A or B or both for the read and write accesses while storing the data in one of the FIFOs.

Choice of Port A or Port B for a certain channel depends on the addresses chosen for the transfer and

should be made by referring to DMA Ports to System Resources Mapping. All DMA memory and register

accesses are performed in user mode. If the DMA writes to registers which are only accessible in

privileged mode, the write will not be performed.

The DMA registers and its local RAM can only be accessed in privilege mode. Therefore, it is not possible

for the DMA to reprogram itself.

In order to further explain DMA operation, some terms are described below:

• Arbitration - A channel may get temporarily suspended in order to service a higher priority channel or

when the channel is disabled on the fly. The channel is said to have been "arbitrated"

• Arbitration Boundary - Each time a channel finishes a chunk of transfer which can be a maximum of 32

bytes, it is said to have reached an arbitration boundary. The FIFO is empty at an arbitration boundary.

The DMA will utilize this boundary to re-prioritize channels. Within an arbitration boundary, transfers

can never be interrupted.

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SPNU562–May 2014 Direct Memory Access Controller (DMA) Module

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