Datasheet

Event manager (prioritization,
arbitration)
DMA req sync
and polarity
FIFO A channel
processing
FIFO B channel
processing
Port Arbiter
Control Packet
Access Arbiter
Control
Regs
Control
Packet
RAM
Interrupt
Manager
Port A Port B
BTC, FTC, BER,
LFS, HBC, MPV
interrupts
CPU I/F
Errors (Single,
Double Bit Errors)
Hardware Events
Overview www.ti.com
Figure 20-1. DMA Block Diagram
20.1.2 System Resources Mapping
DMA Ports to System Resources Mapping shows how the system resources are mapped to either of the
two DMA ports. In order to properly transfer data from one resource to another the application must setup
the PARx register according to the below table.
DMA Ports to System Resources Mapping
DMA Ports System Resources
• L2 Flash
Port A
• L2 SRAM
• EMIF
• All peripherals, i.e. MibSPI registers, DCAN registers
Port B
• All peripheral memories, i.e. MibSPI RAM, DCAN RAM
• Example 1: To transfer data from either L2 Flash, L2 SRAM or EMIF to any peripheral registers or
peripheral memories, write 0x1 (Port A read, Port B write ) to the respective channels in the PARx
registers
• Example 2: To transfer data from any peripheral registers or peripheral memories to L2 SRAM or
EMIF, write 0x0 (Port B read, Port A write ) to the respective channels in the PARx registers
• EXample 3: To transfer data from L2 Flash to L2 SRAM, write 0x2 (Port A) to the respective channels
in the PARx registers
• Example 4: To transfer data from peripherals to another peripherals, write 0x3 (Port B) to the
678
Direct Memory Access Controller (DMA) Module SPNU562–May 2014
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated