Datasheet

VIM Control Registers

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19.9.15 IRQ Interrupt Vector Register (IRQVECREG)

The interrupt vector register gives the address of the enabled and active IRQ interrupt. Figure 19-43 and

Table 19-20 describe these registers.

Figure 19-43. IRQ Interrupt Vector Register (IRQVECREG) [offset = 70h]

31 0

IRQVECREG

R-0

LEGEND: R = Read only; -n = value after reset

Table 19-20. IRQ Interrupt Vector Register (IRQVECREG) Field Descriptions

Bit Field Value Description

31-0 IRQVECREG From IRQ interrupt vector register. This vector gives the address of the ISR with the highest

Section 19.5 pending IRQ request. The CPU reads the address and branches to this location.

19.9.16 FIQ Interrupt Vector Register (FIQVECREG)

The interrupt vector register gives the address of the enabled and active FIQ interrupt. Figure 19-44 and

Table 19-21 describe these registers.

Figure 19-44. IRQ Interrupt Vector Register (FIQVECREG) [offset = 74h]

31 0

FIQVECREG

R-0

LEGEND: R = Read only; -n = value after reset

Table 19-21. FIQ Interrupt Vector Register (FIQVECREG) Field Descriptions

Bit Field Value Description

31-0 FIQVECREG From FIQ interrupt vector register. This vector gives the address of the ISR with the highest

Section 19.5 pending FIQ request. The CPU reads the address and branches to this location.

672

Vectored Interrupt Manager (VIM) Module SPNU562–May 2014

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