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VIM Control Registers

19.9.14 Wake-Up Enable Clear Registers (WAKEENACLR[0:3])

The wake-up enable register selectively disables individual wake-up interrupt request lines. Figure 19-39,

Figure 19-40, Figure 19-41, Figure 19-42 and Table 19-19 describe these registers.

Figure 19-39. Wake-Up Enable Clear Register 0 (WAKEENACLR0) [offset = 60h]

31 0

WAKEENACLR[31:0]

R/WP-FFFF FFFFh

LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset

Figure 19-40. Wake-Up Enable Clear Register 1 (WAKEENACLR1) [offset = 64h]

31 0

WAKEENACLR[63:32]

R/WP-FFFF FFFFh

LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset

Figure 19-41. Wake-Up Enable Clear Register 2 (WAKEENACLR2) [offset = 68h]

31 0

WAKEENACLR[95:64]

R/WP-FFFF FFFFh

LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset

Figure 19-42. Wake-Up Enable Clear Register 3 (WAKEENACLR3) [offset = 6Ch]

31 0

WAKEENACLR[127:96]

R/WP-FFFF FFFFh

LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset

Table 19-19. Wake-Up Enable Clear Registers (WAKEENACLR) Field Descriptions

Bit Field Value Description

127-0 WAKEENACLR[n] Wake-up enable clear bits. This vector determines whether the wake-up interrupt line is

enabled. Bit WAKEENACLRx[127:0] corresponds to interrupt request channel[127:0].

0 Read: Wake-up interrupt channel is disabled.

Write: No effect.

1 Read: The wake-up interrupt channel is enabled.

Write: The wake-up interrupt channel is disabled.

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SPNU562–May 2014 Vectored Interrupt Manager (VIM) Module

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