Datasheet

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19.9.12 Interrupt Enable Clear Registers (REQENACLR[0:3])
The interrupt register enable selectively disables individual request channels. Figure 19-31, Figure 19-32,
Figure 19-33, Figure 19-34 and Table 19-17 describe these registers.
NOTE: Channel 0 and 1 are always enabled, not impacted by this register.
Figure 19-31. Interrupt Enable Clear Register 0 (REQENACLR0) [offset = 40h]
31 16
REQENACLR[31:16]
R/WP-0
15 2 1 0
REQENACLR[15:2] Reserved
R/WP-0 R-3h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 19-32. Interrupt Enable Clear Register 1 (REQENACLR1) [offset = 44h]
31 0
REQENACLR[63:32]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Figure 19-33. Interrupt Enable Clear Register 2 (REQENACLR2) [offset = 48h]
31 0
REQENACLR[95:64]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Figure 19-34. Interrupt Enable Clear Register 3 (REQENACLR3) [offset = 4Ch]
31 0
REQENACLR[127:96]
R/WP-0
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 19-17. Request Enable Clear Registers (REQENACLR) Field Descriptions
Bit Field Value Description
127-2 REQENACLR[n] Request enable clear bits.This vector determines whether the interrupt request channel is
enabled. Bit REQENACLRx[127:2] corresponds to request channel[127:2].
0 Read: Interrupt request channel is disabled.
Write: No effect.
1 Read: The interrupt request channel is enabled.
Write: The interrupt request channel is disabled.
1-0 Reserved 3h Read only. Writes have no effect.
669
SPNU562–May 2014 Vectored Interrupt Manager (VIM) Module
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