Datasheet

www.ti.com VIM Control Registers
19.9.10 Pending Interrupt Read Location Registers (INTREQ[0:3])
The pending interrupt register gives the pending interrupt requests. The register is updated every vbus
clock cycle. Figure 19-23, Figure 19-24, Figure 19-25, Figure 19-26 and Table 19-15 describe this
register.
Figure 19-23. Pending Interrupt Read Location Register 0 (INTREQ0) [offset = 20h]
31 0
INTREQ[31:0]
R/W1CP-0
LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -n = value after reset
Figure 19-24. Pending Interrupt Read Location Register 1 (INTREQ1) [offset = 24h]
31 0
INTREQ[63:32]
R/W1CP-0
LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -n = value after reset
Figure 19-25. Pending Interrupt Read Location Register 2 (INTREQ2) [offset = 28h]
31 0
INTREQ[95:64]
R/W1CP-0
LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -n = value after reset
Figure 19-26. Pending Interrupt Read Location Register 3 (INTREQ3) [offset = 2Ch]
31 0
INTREQ[127:96]
R/W1CP-0
LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -n = value after reset
Table 19-15. Pending Interrupt Read Location Registers (INTREQ) Field Descriptions
Bit Field Value Description
127-0 FIRQPR[n] Pending interrupt bits. These bits determine whether an interrupt request is pending for the request
channel between 0 and 127. The interrupt ENABLE register does not affect the value of the
interrupt pending bit. Bit INTREQx[127:0] corresponds to request channel[127:0].
User and Privilege Mode read:
0 No interrupt event has occurred.
1 An interrupt is pending.
Privilege Mode write only:
0 Writing 0 has no effect.
1 Clears the "interrupt pending" status flag. This write-clear functionality is intended to allow clearing
those interrupts which have been signaled to VIM before enabling the interrupt channel, if they are
undesired.
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SPNU562–May 2014 Vectored Interrupt Manager (VIM) Module
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