Datasheet

www.ti.com VIM Control Registers
19.9.7 IRQ Index Offset Vector Register (IRQINDEX)
The IRQ offset register provides the user with the numerical index value that represents the pending IRQ
interrupt with the highest priority. Figure 19-17 and Table 19-12 describe this register.
Figure 19-17. IRQ Index Offset Vector Register (IRQINDEX) [offset = 00h]
31 16
Reserved
R-0
15 8 7 0
Reserved IRQINDEX
R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 19-12. IRQ Index Offset Vector Register (IRQINDEX) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Read returns 0. Writes have no effect.
7-0 IRQINDEX 0-FFh IRQ index vector. The least significant bits represent the index of the IRQ pending interrupt
with the highest precedence, as shown in Table 19-11. When no interrupts are pending, the
least significant byte of IRQINDEX is 0.
19.9.8 FIQ Index Offset Vector Registers (FIQINDEX)
The FIQINDEX register provides the user with a numerical index value that represents the pending FIQ
interrupt with the highest priority. Figure 19-18 and Table 19-13 describe this register.
Figure 19-18. FIQ Index Offset Vector Register (FIQINDEX) [offset = F04h]
31 16
Reserved
R-0
15 8 7 0
Reserved FIQINDEX
R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 19-13. FIQ Index Offset Vector Register (FIQINDEX) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Read returns 0. Writes have no effect.
7-0 FIQINDEX 0-FFh FIQ index offset vector. The least significant bits represent the index of the FIQ pending
interrupt with the highest precedence, as shown in Table 19-11. When no interrupts are
pending, the least significant byte of FIQINDEX is 0x00.
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SPNU562–May 2014 Vectored Interrupt Manager (VIM) Module
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