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VIM Control Registers

19.9.3 Uncorrectable Error Address Register (UERRADDR)

The uncorrectable error address register gives the address of the first uncorrectable error location.

NOTE: No computation is needed when reading the complete register to retrieve the address in the

Interrupt Vector Table.

This register will never be reset by a power-on reset nor any other reset source.

Figure 19-14. Uncorrectable Error Address Register (UERRADDR) [offset = F4h]

31 16

Interrupt Vector Table offset

R-FFF8h

15 10 9 2 1 0

Interrupt Vector Table offset ADDERR Word offset

R-10h R-x R-0

LEGEND: R = Read only; -n = value after reset

Table 19-8. Uncorrectable Error Address Register (UERRADDR) Field Descriptions

Bit Field Description

31-10 Interrupt Vector Table Interrupt Vector Table offset. Reads are always FF F820h; writes have no effect

offset

9-2 ADDERR Uncorrectable error address register. This register gives the address of the first encountered double bit

error since the flag has been clear. Subsequent ECC errors will not update this register until the UERR

flag has been cleared.

Note: This register is valid only when PARFLG is set (see Section 19.9.1).

1-0 Word offset Word offset. Reads are always 0; writes have no effect.

19.9.4 Fallback Vector Address Register (FBVECADDR)

This register provides a fall-back address to the VIM if a uncorrectable error has occurred in the Interrupt

Vector Table. Figure 19-15 and Table 19-9 describe this register.

NOTE: This register will never be reset by a power-on reset nor any other reset source.

Figure 19-15. Fallback Vector Address Register (FBVECADDR) [offset = F8h]

31 0

FBVECADDR

R/WP-x

LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset; x = Indeterminate

Table 19-9. Fallback Vector Address Register (FBVECADDR) Field Descriptions

Bit Field Description

31-0 FBVECADDR Fallback Vector Address Register. This register is used by the VIM if the Interrupt Vector Table has been

corrupted. The contents of the IRQVECREG and FIQVECREG registers will reflect the value programmed

in FBVECADDR. The value provided to the VIC port will also reflect FBVECADDR until the UERR register

has been cleared.

This register provides the address of the ISR that will restore the integrity of the Interrupt Vector Table.

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SPNU562–May 2014 Vectored Interrupt Manager (VIM) Module

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