Datasheet

Word 0

Word 1

Word 2

Word 3

ECC0

ECC2

ECC3

32-bit only accessible

0xFFF82000

0xFFF82400

ECC1

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Interrupt Vector Table (VIM RAM)

Following sequence should be used for injecting faults to data bits and testing the ECC check feature.

1. Write the data locations of VIM RAM with the required patterns while keeping ECCENA active. The

ECC bits will be automatically initialized along with data bits.

2. Disable ECC by setting ECCENA=0 in ECCCTRL register. In this mode, writing to data bits does not

automatically update ECC bits.

3. In this mode, it is possible to corrupt data bits using any of the following methods.

• Read the data bits, flip one bit and write back

• Read the data bits, flip 2 bits and write back

4. Depending on the kind corruption created, read back the data bits and check for the correction error

(single bit error or double bit error or no error).

5. Read the UERRADDR and SBERRADDR registers and check for the correct address capture as well.

NOTE: After completing the tests for ECC check features, it should be ensured that VIM Interrupt

Vector Table is initialized with valid data and corresponding check bits. Care should also be

taken to clear the UERR and SBERR flag registers and the error address registers.

Figure 19-9. ECC Bits Mapping

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SPNU562–May 2014 Vectored Interrupt Manager (VIM) Module

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