Datasheet

www.ti.com Interrupt Vector Table (VIM RAM)
When a read occurs from the CPU or VIM, the VIM calculates the ECC bits from the data coming from the
interrupt vector table and compares it to the known good ECC value stored in the table. If a single bit error
is detected in the data, the SECDED block will automatically correct it. The read data will be a corrected
one in this case. If double bit errors are detected, the read data will be the uncorrected one. The access of
the data and the ECC bits are performed in the same clock cycle.
The Double Bit Error (DBE) and Single Bit Error (SBE) events will be generated only if the ECC feature is
enabled by ECCENA field. Correction of the data upon a SBE event will be done only if enabled
EDAC_MODE field. Any double bit error will be flagged out to ESM module and as UERR flag in
ECCSTAT register. The address of the data for which UERR is detected will also be stored as
UERRADDR register.
Any single bit error will be registered into SBERR flag in ECCSTAT register and the corresponding
address will be captured as SBERRADDR register. If SBE_INT_EN field on ECCCTL register is set to
enable value, then it will be flagged out to ESM module.
Since the interrupt vector table may have an uncorrectable error (e.g. DBE), the FBVECADDR register will
provide to the VIC port, IRQVECREG and FIQVECREG, a fall-back address to an ISR that can restore the
interrupt vector table content. The FB_VECADDR register should be set before intializing the interrupt in
the interrupt vector table, to avoid branching to an unpredictable location.
The normal operation is restored when the ECCSTAT is cleared by the CPU. It is recommended to restore
the content of the VIM before clearing the ECCSTAT.
19.5.2 VIM ECC Syndrome
The VIM ECC is controlled by the ECCENA bits of ECCCTL register. After reset, the SECDED feature is
disabled. The SECDED feature can be enabled by writing 0xA (1010b) in the ECCENA[3:0] bit field of the
ECCCTL register.
The ECC generation is done according to the ECC syndrome table as shown in Table 19-1 and Table 19-
2. Each ECC bit is build by generating the parity of the 'XOR'ed bits of the data word, whereas ECC bit 2
and 3 are even parity and the other bits odd parity
Table 19-1. ECC Syndrome Table
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 ECC
x x x x x x x x x x x x x x x x 6
x x x x x x x x x x x x x x x x 5
x x x x x x x x x x x x x x x x 4
x x x x x x x x x x x x x x x x 3
x x x x x x x x x x x x x x x x 2
x x x x x x x x x x x x x x x x 1
x x x x x x x x x x x x x x x x 0
Table 19-2. ECC Error Bits for Syndrome Decode
6 5 4 3 2 1 0 ECC
x 6
x 5
x 4
x 3
x 2
x 1
x 0
653
SPNU562–May 2014 Vectored Interrupt Manager (VIM) Module
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