Datasheet

Phantom Vector
Channel 0 Vector
Channel 1 Vector
Channel 125 Vector
Channel 126 Vector
0xFFF821FC
0xFFF821F8
0xFFF82008
0xFFF82004
0xFFF82000
Interrupt vector table address space
Interrupt Vector Table (VIM RAM) www.ti.com
After the VIM has generated the vector corresponding to the highest active IRQ, it updates the FIQINDEX
or the IRQINDEX register, depending on the class of interrupt. Then, it accesses the interrupt vector table
using the vector value to fetch the address of the corresponding ISR. If the request is an FIQ class
interrupt, the address read from the interrupt vector table, is written to the FIQVECREG register. If the
request is an IRQ class interrupt, the address is written to the IRQVECREG register and put on the VIC
port of the CPU (in case of hardware vectored interrupt is enabled).
All of the interrupt registers are updated when a new high priority interrupt line becomes active.
19.5 Interrupt Vector Table (VIM RAM)
Interrupt vector table stores the address of ISRs. During register vectored interrupt and hardware vectored
interrupt, VIM accesses the interrupt vector table using the vector value to fetch the address of the
corresponding ISR.
For safety reasons, the interrupt vector table has protection by ECC to indicate corruption due to soft
errors. The ECC scheme is implemented as a continuous background check based on memory access.
The ECC logic inside VIM supports Single bit Error Correction and Double bit Error Detection (SECDED).
Section 19.5.1 through Section 19.5.4 describe how ECC works in the interrupt vector table.
19.5.1 Interrupt Vector Table Operation
The interrupt vector table is organized in 128 words of 32 bits. Figure 19-8 shows the interrupt memory
mapping. The table base address is 0xFFF82000.
Figure 19-8. VIM Interrupt Address Memory Map
NOTE: The interrupt vector table only has 128 entries, one phantom vector and 127 interrupt
channels. Channel 127 does not have a dedicated vector and shall not be used.
There are seven bits of ECC per 32-bit ISR address. When a write is performed into the interrupt vector
table, the ECC bits are calculated for the 32-bit word and written into the corresponding ECC region of
interrupt vector table if ECC is enabled in VIM.
NOTE: Only 32-bit write/read access are allowed on interrupt vector table if ECC is required. Non
32-bit access might result in ECC errors.
652
Vectored Interrupt Manager (VIM) Module SPNU562–May 2014
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