Datasheet

www.ti.com CRC Control Registers
18.4.23 CRC Sector Counter Preload Register 2 (CRC_SCOUNT_REG2)
Figure 18-31. CRC Sector Counter Preload Register 2 (CRC_SCOUNT_REG2) [offset = 84h]
31 16
Reserved
R-0
15 0
CRC_SEC_COUNT2
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-27. CRC Sector Counter Preload Register 2 (CRC_SCOUNT_REG2) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reads return 0. Writes have no effect.
15-0 CRC_SEC_COUNT2 Channel 2 Sector Counter Preload Register.This register contains the number of sectors
in one block of memory.
18.4.24 CRC Current Sector Register 2 (CRC_CURSEC_REG2)
Figure 18-32. CRC Current Sector Register 2 (CRC_CURSEC_REG2) [offset = 88h]
31 16
Reserved
R-0
15 0
CRC_CURSEC2
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-28. CRC Current Sector Register 2 (CRC_CURSEC_REG2) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reads return 0. Writes have no effect.
15-0 CRC_CURSEC2 Channel 2 Current Sector ID Register. In AUTO mode, this register contains the current
sector number of which the signature verification fails. The sector counter is a free running
up counter. When a sector fails, the erroneous sector number is logged into current sector
ID register and the CRC fail interrupt is generated The sector ID register is frozen until it is
read and the CRC fail status bit is cleared by CPU. While it is frozen, it does not capture
another erroneous sector number. When this condition happens, an overrun interrupt is
generated instead. Once the register is read and the CRC fail interrupt flag is cleared it can
capture new erroneous sector number. In Semi-CPU mode, this register is used to indicate
the sector number for which the compression complete has last happened.
637
SPNU562–May 2014 Cyclic Redundancy Check (CRC) Controller Module
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated