Datasheet

f[MHz]
1.375 4.875 22 78
fail
lower
threshold
pass
upper
threshold
fail
86
RM57L843
SPNS215C –FEBRUARY 2014–REVISED JUNE 2016 www.ti.com
Submit Documentation Feedback
Product Folder Links: RM57L843
System Information and Electrical Specifications Copyright © 2014–2016, Texas Instruments Incorporated
6.7 Clock Monitoring
The LPO Clock Detect (LPOCLKDET) module consists of a clock monitor (CLKDET) and an internal LPO.
The LPO provides two different clock sources – a low frequency (CLK80K) and a high frequency
(CLK10M).
The CLKDET is a supervisor circuit for an externally supplied clock signal (OSCIN). In case the OSCIN
frequency falls out of a frequency window, the CLKDET flags this condition in the global status register
(GLBSTAT bit 0: OSC FAIL) and switches all clock domains sourced by OSCIN to the CLK10M clock (limp
mode clock).
The valid OSCIN frequency range is defined as: f
CLK10M
/ 4 < f
OSCIN
< f
CLK10M
* 4.
6.7.1 Clock Monitor Timings
Figure 6-8. LPO and Clock Detection, Untrimmed CLK10M
6.7.2 External Clock (ECLK) Output Functionality
The ECLK1/ECLK2 terminal can be configured to output a prescaled clock signal indicative of an internal
device clock. This output can be externally monitored as a safety diagnostic.
6.7.3 Dual Clock Comparators
The Dual Clock Comparator (DCC) module determines the accuracy of selectable clock sources by
counting the pulses of two independent clock sources (counter 0 and counter 1). If one clock is out of
spec, an error signal is generated. For example, the DCC1 can be configured to use CLK10M as the
reference clock (for counter 0) and VCLK as the "clock under test" (for counter 1). This configuration
allows the DCC1 to monitor the PLL output clock when VCLK is using the PLL output as its source.
An additional use of this module is to measure the frequency of a selectable clock source. For example,
the reference clock is connected to Counter 0 and the signal to be measured is connected to Counter 1.
Counter 0 is programmed with a start value of known time duration (measurement time) from the
reference clock. Counter 1 is programmed with a maximum start value. Start both counter simultaneously.
When Counter 0 decrements to zero, both counter will stop and an error signal is generated if Counter 1
does not reach zero. The frequency of the input signals can be calculated from the count value of Counter
1 and the measurement time.
6.7.3.1 Features
• Takes two different clock sources as input to two independent counter blocks.
• One of the clock sources is the known-good, or reference clock; the second clock source is the "clock under test."
• Each counter block is programmable with initial, or seed values.
• The counter blocks start counting down from their seed values at the same time; a mismatch from the expected
frequency for the clock under test generates an error signal which is used to interrupt the CPU.