Datasheet

CRC Control Registers www.ti.com
18.4.10 CRC Sector Counter Preload Register 1 (CRC_SCOUNT_REG1)
Figure 18-18. CRC Sector Counter Preload Register 1 (CRC_SCOUNT_REG1) [offset = 44h]
31 16
Reserved
R-0
15 0
CRC_SEC_COUNT1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-14. CRC Sector Counter Preload Register 1 (CRC_SCOUNT_REG1) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reads return 0. Writes have no effect.
15-0 CRC_SEC_COUNT1 Channel 1 Sector Counter Preload Register. This register contains the number of sectors
in one block of memory.
18.4.11 CRC Current Sector Register 1 (CRC_CURSEC_REG1)
Figure 18-19. CRC Current Sector Preload Register 1 (CRC_CURSEC_REG1) [offset = 48h]
31 16
Reserved
R-0
15 0
CRC_CURSEC1
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-15. CRC Current Sector Register 1 (CRC_CURSEC_REG1) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reads return 0. Writes have no effect.
15-0 CRC_CURSEC1 Channel 1 Current Sector ID Register. In AUTO mode, this register contains the current
sector number of which the signature verification fails. The sector counter is a free running up
counter. When a sector fails, the erroneous sector number is logged into current sector ID
register and the CRC fail interrupt is generated The sector ID register is frozen until it is read
and the CRC fail status bit is cleared by CPU. While it is frozen, it does not capture another
erroneous sector number. When this condition happens, an overrun interrupt is generated
instead. Once the register is read and the CRC fail interrupt flag is cleared it can capture new
erroneous sector number. In Semi-CPU mode, this register is used to indicate the sector
number for which the compression complete has last happened.
632
Cyclic Redundancy Check (CRC) Controller Module SPNU562–May 2014
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