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CRC Control Registers www.ti.com
18.4.5 CRC Interrupt Enable Reset Register (CRC_INTR)
Figure 18-13. CRC Interrupt Enable Reset Register (CRC_INTR) [offset = 20h]
31 16
Reserved
R-0
15 13 12 11 10 9 8
Reserved CH2_ CH2_ CH2_ CH2_ CH2_
TIMEOUTENR UNDERENR OVERENR CRCFAILENR CCITENR
R-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0
7 5 4 3 2 1 0
Reserved CH1_ CH1_ CH1_ CH1_ CH1_
TIMEOUTENR UNDERENR OVERENR CRCFAILENR CCITENR
R-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 18-9. CRC Interrupt Enable Reset Register (CRC_INTR) Field Descriptions
Bit Field Value Description
31-13 Reserved 0 Reads return 0. Writes have no effect.
12 CH2_TIMEOUTENR Channel 2 Timeout Interrupt Enable Reset Bit.
User and Privileged mode (read):
0 Timeout Interrupt is disabled
1 Timeout Interrupt is enabled
Privileged mode (write):
0 No effect
1 Timeout Interrupt disable
11 CH2_UNDERENR Channel 2 Underrun Interrupt Enable Reset Bit.
User and Privileged mode (read):
0 Underrun Interrupt is disabled
1 Underrun Interrupt is enabled
Privileged mode (write):
0 No effect
1 Underrun Interrupt disable
10 CH2_OVERENR Channel 2 Overrun Interrupt Enable Reset Bit.
User and Privileged mode (read):
0 Overrun Interrupt is disabled
1 Overrun Interrupt is enabled
Privileged mode (write):
0 No effect
1 Overrun Interrupt disable
9 CH2_CRCFAILENR Channel 2 CRC Compare Fail Interrupt Enable Reset Bit.
User and Privileged mode (read):
0 CRC Fail Interrupt disable
1 CRC Fail Interrupt is enabled
Privileged mode (write):
0 No effect
1 CRC Fail Interrupt disable
626
Cyclic Redundancy Check (CRC) Controller Module SPNU562–May 2014
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