Datasheet

CRC Control Registers www.ti.com
18.4.4 CRC Interrupt Enable Set Register (CRC_INTS)
Figure 18-12. CRC Interrupt Enable Set Register (CRC_INTS) [offset = 18h]
31 16
Reserved
R-0
15 13 12 11 10 9 8
Reserved CH2_ CH2_ CH2_ CH2_ CH2_
TIMEOUTENS UNDERENS OVERENS CRCFAILENS CCITENS
R-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0
7 5 4 3 2 1 0
Reserved CH1_ CH1_ CH1_ CH1_ CH1_
TIMEOUTENS UNDERENS OVERENS CRCFAILENS CCITENS
R-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 18-8. CRC Interrupt Enable Set Register (CRC_INTS) Field Descriptions
Bit Field Value Description
31-13 Reserved 0 Reads return 0. Writes have no effect.
12 CH2_TIMEOUTENS Channel 2 Timeout Interrupt Enable Bit.
User and Privileged mode (read):
0 Timeout Interrupt is disabled
1 Timeout Interrupt is enabled
Privileged mode (write):
0 No effect
1 Timeout Interrupt enable
11 CH2_UNDERENS Channel 2 Underrun Interrupt Enable Bit.
User and Privileged mode (read):
0 Underrun Interrupt is disabled
1 Underrun Interrupt is enabled
Privileged mode (write):
0 No effect
1 Underrun Interrupt enable
10 CH2_OVERENS Channel 2 Overrun Interrupt Enable Bit.
User and Privileged mode (read):
0 Overrun Interrupt is disabled
1 Overrun Interrupt is enabled
Privileged mode (write):
0 No effect
1 Overrun Interrupt enable
9 CH2_CRCFAILENS Channel 2 CRC Compare Fail Interrupt Enable Bit.
User and Privileged mode (read):
0 CRC Fail Interrupt is disabled
1 CRC Fail Interrupt is enabled
Privileged mode (write):
0 No effect
1 CRC Fail Interrupt enable
624
Cyclic Redundancy Check (CRC) Controller Module SPNU562–May 2014
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