Datasheet

VCLKA4_SRC
0
1
3
4
5
6
7
VCLK
VCLKA4 (left open)
/DIVR
PLL2 post_ODCLK/8
PLL2 post_ODCLK/16
VCLKA4_DIVR_EMAC
(to EMAC)
83
RM57L843
www.ti.com SPNS215C –FEBRUARY 2014–REVISED JUNE 2016
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System Information and Electrical SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
6.6.3 Special Clock Source Selection Scheme for VCLKA4_DIVR_EMAC
The MII interface requires VCLKA4_DIVR_EMAC to be 25 MHz and the RMII requires
VCLKA4_DIVR_EAMC to be 50 MHz.
These different frequencies are supported by adding special dedicated clock source selection options for
the VCLKA4_DIVR_EMAC clock domain. This logic is shown in Figure 6-7.
Figure 6-7. VCLKA4_DIVR Source Selection Options
The PLL2 post_ODCLK is brought out as a separate output from the PLL wrapper module. There are two
additional dividers implemented at the device-level to divide this PLL2 post_ODCLK by 8 and by 16.
As shown in Figure 6-7, the VCLKA4_SRC configured through the system module VCLKACON1 control
register is used to determine the clock source for the VCLKA4 and VCLKA4_DIVR. An additional
multiplexor is implemented to select between the VCLKA4_DIVR and the two additional clock sources –
PLL2 post_ODCLK/8 and post_ODCLK/16.
Table 6-17 lists the VCLKA4_DIVR_EMAC clock source selections.
Table 6-17. VCLKA4_DIVR_EMAC Clock Source Selection
VCLKA4_SRC FROM VCLKACON1[19–16] CLOCK SOURCE FOR VCLKA4_DIVR_EMAC
0x0 OSCIN / VCLKA4R
0x1 PLL1CLK / VCLKA4R
0x2 Reserved
0x3 EXTCLKIN1 / VCLKA4R
0x4 LF LPO / VCLKA4R
0x5 HF LPO / VCLKA4R
0x6 PLL2CLK / VCLKA4R
0x7 EXTCLKIN2 / VCLKA4R
0x8–0xD VCLK
0xE PLL2 post_ODCLK/8
0xF PLL2 post_ODCLK/16