Datasheet

HCLK1 (to SYSTEM)
GCLK, GCLK2 (to CPU, CCM)
GCM
VCLK (VCLK to peripherals on PCR3)
RTICLK1 (to RTI1, DWWD)
/1, 2, 4, or 8
VCLK
OSCIN
Low Power
Oscillator
10MHz
80kHz
FMzPLL
1
0
4
5
/1..64
X1..256
/1..8
/1..32
6
PLL # 2
*
VCLK
/1,2,..1024
Phase_seg2
CAN Baud Rate
Phase_seg1
VCLKA1
/1,2,..256
SPIx,MibSPIx
/2,3..2
24
LIN, SCI
SPI
LIN / SCI
/1,2..32
MibADCx
ADCLK
/1,2..65536
External Clock
ECLK
VCLK2
N2HETx
HRP
/1..64
LRP
/2
0
..2
5
Loop
Resolution Clock
High
Baud Rate
Baud Rate
N2HETx
TU
VCLK2
Ethernet
VCLKA4_DIVR
(SSPLL)
(SSPLL)
/1..64 X1..256 /1..8
/1..32 *
EXTCLKIN1
EXTCLKIN2
3
7
VCLKA1 (to DCANx)
CLKSRC(7:0)
VCLK
VCLK3
EMIF
VCLK3 (to EMIF, , ePWMx,
and eQEPx)
eCAPx
Ethernet
/1..16
VCLK_s (VCLK to system modules)
* the frequency at this node must not
exceed the maximum HCLK specifiation.
/1,2..256
I2C
I2C baud
rate
VCLKA2
NTU[1]
NTU[0]
NTU[2]
NTU[3]
RTI
Reserved
PLL#2 output
EXTCLKIN1
Prop_seg
DCANx
VCLK2 (to N2HETx and HTUx)
VCLKA4_DIVR_EMAC (to Ethernet,
as alternate for MIIXCLK and/or
MIIRXCLK) VCLKA4 is left open.
CLKSRC(7:0)
VCLK
CLKSRC(7:0)
VCLK
CLKSRC(7:0)
/1..16
/1..16
/1..16
/1..4
Reserved
82
RM57L843
SPNS215C –FEBRUARY 2014–REVISED JUNE 2016 www.ti.com
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System Information and Electrical Specifications Copyright © 2014–2016, Texas Instruments Incorporated
6.6.2.2 Mapping of Clock Domains to Device Modules
Each clock domain has a dedicated functionality as shown in Figure 6-6.
Figure 6-6. Device Clock Domains