Datasheet

Control Registers www.ti.com
Table 17-27. RTI Clear Interrupt Control Register (RTICLEARINTENA) Field Descriptions (continued)
Bit Field Value Description
9 CLEARDMA1 Clear compare DMA request 1.
0 Read: DMA request is disabled.
Write: Corresponding bit is unchanged.
1 Read: DMA request is enabled.
Write: DMA request is disabled.
8 CLEARDMA1 Clear compare DMA request 0.
0 Read: DMA request is disabled.
Write: Corresponding bit is unchanged.
1 Read: DMA request is enabled.
Write: DMA request is disabled.
7-4 Reserved 0 Reads return 0. Writes have no effect.
3 CLEARINT3 Clear compare interrupt 3.
0 Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.
1 Read: Interrupt is enabled.
Write: Interrupt is disabled.
2 CLEARINT2 Clear compare interrupt 2.
0 Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.
1 Read: Interrupt is enabled.
Write: Interrupt is disabled.
1 CLEARINT1 Clear compare interrupt 1.
0 Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.
1 Read: Interrupt is enabled.
Write: Interrupt is disabled.
0 CLEARINT0 Clear compare interrupt 0.
0 Read: Interrupt is disabled.
Write: Corresponding bit is unchanged.
1 Read: Interrupt is enabled.
Write: Interrupt is disabled.
594
Real-Time Interrupt (RTI) Module SPNU562–May 2014
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated