Datasheet

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17.3.17 RTI Compare 1 Register (RTICOMP1)
The compare 1 register holds the value to be compared to the counters. This register is shown in
Figure 17-28 and described in Table 17-18.
Figure 17-28. RTI Compare 1 Register (RTICOMP1) [offset = 58h]
31 16
COMP1
R/WP-0
15 0
COMP1
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 17-18. RTI Compare 1 Register (RTICOMP1) Field Descriptions
Bit Field Value Description
31-0 COMP1 0-FFFF FFFFh Compare 1. This register holds a value that is compared with the counter selected in the
compare control logic. If RTIFRC0 or RTIFRC1, depending on the counter selected, matches
this compare value, an interrupt is flagged. With this register, it is possible to initiate a DMA
request.
A read of this register will return the current compare value.
A write to this register will update the compare register with a new compare value.
17.3.18 RTI Update Compare 1 Register (RTIUDCP1)
The update compare 1 register holds the value to be added to the compare register 1 value on a compare
match. This register is shown in Figure 17-29 and described in Table 17-19.
Figure 17-29. RTI Update Compare 1 Register (RTIUDCP1) [offset = 5Ch]
31 16
UDCP1
R/WP-0
15 0
UDCP1
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 17-19. RTI Update Compare 1 Register (RTIUDCP1) Field Descriptions
Bit Field Value Description
31-0 UDCP1 0-FFFF FFFFh Update compare 1. This register holds a value that is added to the value in the RTICOMP1
register each time a compare matches. This process allows periodic interrupts to be generated
without software intervention.
A read of this register will return the value to be added to the RTICOMP1 register on the next
compare match. .
A write to this register will provide a new update value
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SPNU562–May 2014 Real-Time Interrupt (RTI) Module
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