Datasheet

81
RM57L843
www.ti.com SPNS215C –FEBRUARY 2014–REVISED JUNE 2016
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System Information and Electrical SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
Table 6-16. Clock Domain Descriptions (continued)
CLOCK DOMAIN CLOCK DISABLE BIT
DEFAULT
SOURCE
SOURCE SELECTION
REGISTER
SPECIAL CONSIDERATIONS
VCLKA4_DIVR SYS.VCLKACON1.20 VCLK SYS.VCLKACON1[19:16]
• Divided down from VCLKA4 using the
VCLKA4R field of the VCLKACON1
register
• Frequency can be VCLKA4/1,
VCLKA4/2, ..., or VCLKA4/8
• Default frequency is VCLKA4/2
• Is disabled separately through the
VCLKA4_DIV_CDDIS bit in the
VCLKACON1 register, if the VCLKA4 is
not already disabled
RTICLK1 SYS.CDDIS.6 VCLK SYS.RCLKSRC[3:0]
• Defaults to VCLK as the source
• If a clock source other than VCLK is
selected for RTICLK1, then the RTICLK1
frequency must be less than or equal to
VCLK/3
• Application can ensure this by
programming the RTI1DIV field of the
RCLKSRC register, if necessary
• Is disabled through the CDDISx registers
bit 6