Datasheet

www.ti.com ESM Control Registers
16.4.11 ESM Interrupt Offset High Register (ESMIOFFHR)
Figure 16-21. ESM Interrupt Offset High Register (ESMIOFFHR) [offset = 28h]
31 16
Reserved
R-0
15 8 7 0
Reserved INTOFFH
R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 16-13. ESM Interrupt Offset High Register (ESMIOFFHR) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Read returns 0. Writes have no effect.
7-0 INTOFFH Offset High Level Interrupt. This vector gives the channel number of the highest pending interrupt
request for the high level interrupt line. Interrupts of error Group2 have higher priority than interrupts
of error Group1. Inside a group, channel 0 has highest priority and channel 31 has lowest priority.
User and privileged mode (read):
Returns number of pending interrupt with the highest priority for the high level interrupt line.
0 No pending interrupt.
1h Interrupt pending for channel 0, error Group1.
: :
20h Interrupt pending for channel 31, error Group1.
21h Interrupt pending for channel 0, error Group2.
: :
40h Interrupt pending for channel 31, error Group2.
41h Interrupt pending for channel 32, error Group1.
: :
60h Interrupt pending for channel 63, error Group1.
61h Reserved
: :
80h Reserved
81h Interrupt pending for channel 64, error Group1.
: :
A0h Interrupt pending for channel 95, error Group1.
Note: Reading the interrupt vector will clear the corresponding flag in the ESMSR2 register; will not
clear ESMSR1 and ESMSSR2 and the offset register gets updated.
User and privileged mode (write):
Writes have no effect.
551
SPNU562–May 2014 Error Signaling Module (ESM)
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