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16.4.5 ESM Interrupt Level Set/Status Register 1 (ESMILSR1)
This register is dedicated for Group1 Channel[31:0].
Figure 16-15. ESM Interrupt Level Set/Status Register 1 (ESMILSR1) [offset = 10h]
31 16
INTLVLSET[31:16]
R/WP-0
15 0
INTLVLSET[15:0]
R/WP-0
LEGEND: R/W = Read/Write; R = Read; WP = Write in privileged mode only; -n = value after reset
Table 16-7. ESM Interrupt Level Set/Status Register 1 (ESMILSR1) Field Descriptions
Bit Field Value Description
31-0 INTLVLSET Set Interrupt Priority
Read in User and Privileged mode. Write in Privileged mode only.
0 Read: Interrupt of channel x is mapped to low level interrupt line.
Write: Leaves the bit and the corresponding clear bit in the ESMILCR1 register unchanged.
1 Read: Interrupt of channel x is mapped to high level interrupt line.
Write: Maps interrupt of channel x to high level interrupt line and sets the corresponding clear bit in
the ESMILCR1 register.
16.4.6 ESM Interrupt Level Clear/Status Register 1 (ESMILCR1)
This register is dedicated for Group1 Channel[31:0].
Figure 16-16. ESM Interrupt Level Clear/Status Register 1 (ESMILCR1) [offset = 14h]
31 16
INTLVLCLR[31:16]
R/WP-0
15 0
INTLVLCLR[15:0]
R/WP-0
LEGEND: R/W = Read/Write; R = Read; WP = Write in privileged mode only; -n = value after reset
Table 16-8. ESM Interrupt Level Clear/Status Register 1 (ESMILCR1) Field Descriptions
Bit Field Value Description
31-0 INTLVLCLR Clear Interrupt Priority.
Read in User and Privileged mode. Write in Privileged mode only.
0 Read: Interrupt of channel x is mapped to low level interrupt line.
Write: Leaves the bit and the corresponding set bit in the ESMILSR1 register unchanged.
1 Read: Interrupt of channel x is mapped to high level interrupt line.
Write: Maps interrupt of channel x to low level interrupt line and clears the corresponding set bit in
the ESMILSR1 register.
548
Error Signaling Module (ESM) SPNU562–May 2014
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