Datasheet

www.ti.com DCC Control Registers
15.4.10 DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC)
Figure 15-15 and Table 15-10 describe the DCC Counter1 Value register.
Figure 15-16. DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC) [offset = 24h]
31 16
Reserved
R-0
15 12 11 4 3 0
KEY Reserved CNT1 CLKSRC
R/WP-5h R-0 R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 15-11. DCC Counter1 Value Register (DCCCNT1) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Read returns 0. Writes have no effect.
15-12 KEY Key to enable clock source selection for Counter1.
Read in any operating mode returns the current value of the key.
Writing in privileged mode sets the key value.
Ah Writing Ah as the key enables the CNT1 CLKSRC field to define the clock source for
counter1.
Any other value Writing any other key value disables the clock source selection for counter1.
Refer the device datasheet for available clock source options and the KEY required to
enable these options for counter1.
11-4 Reserved 0 Read returns 0. Writes have no effect.
3-0 CNT1 CLKSRC Clock Source for Counter1 when KEY is programmed to be Ah.
Read in any operating mode returns the current value of CLKSRC.
Writes in privileged mode select the clock source for Counter1.
Refer the device datasheet for available clock source options and the KEY required to
enable these options for Counter1.
15.4.11 DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC)
Figure 15-15 and Table 15-10 describe the DCC Counter0 Value register.
Figure 15-17. DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC) [offset = 24h]
31 16
Reserved
R-0
15 4 3 0
Reserved CNT0 CLKSRC
R-0 R/WP-5h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 15-12. DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC) Field
Descriptions
Bit Field Value Description
31-4 Reserved 0 Read returns 0. Writes have no effect.
3-0 CNT0 CLKSRC Clock Source for Counter0
Read in any operating mode returns the current value of CLKSRC.
Writes in privileged mode select the clock source for Counter0.
Refer the device datasheet for available clock source options for Counter0.
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SPNU562–May 2014 Dual-Clock Comparator (DCC) Module
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