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DCC Control Registers

15.4.7 DCC Counter0 Value Register (DCCCNT0)

Figure 15-13 and Table 15-8 describe the DCC Counter0 Value register.

Figure 15-13. DCC Counter0 Value Register (DCCCNT0) [offset = 18h]

31 20 19 16

Reserved COUNT0

R-0 R-0

15 0

COUNT0

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15-8. DCC Counter0 Seed Register (DCCCNT0) Field Descriptions

Bit Field Value Description

31-20 Reserved 0 Read returns 0. Writes have no effect.

19-0 COUNT0 Current value of DCC Counter0.

Read in any operating mode returns the current value of Counter0.

Writes have no effect.

NOTE: Reads may not return exact current value of counter

Reading the counter0 value while counting is enabled may not return the exact value of the

counter0.

535

SPNU562–May 2014 Dual-Clock Comparator (DCC) Module

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