Datasheet

www.ti.com DCC Control Registers
15.4.4 DCC Valid0 Seed Register (DCCVALID0SEED)
Figure 15-10 and Table 15-5 describe the DCC Valid0 Seed register.
Figure 15-10. DCC Valid0 Seed Register (DCCVALID0SEED) [offset = Ch]
31 16
Reserved
R-0
15 0
VALID0 SEED
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 15-5. DCC Valid0 Seed Register (DCCVALID0SEED) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Read returns 0. Writes have no effect.
15-0 VALID0 SEED Seed value for DCC Valid0. This value defines the window within which the Counter1 must
reach 0. This window needs to be at least 4 cycles wide.
Read in any operating mode returns the current value of seed for Valid0.
Writing in privileged mode only sets the current seed value for Valid0. Writes in user mode
are ignored.
NOTE: Seed for Valid0 must be at least 0x4
The DCC must only be enabled after programming a value greater than or equal to 0x4 in
the VALID0 SEED register.
15.4.5 DCC Counter1 Seed Register (DCCCNT1SEED)
Figure 15-11 and Table 15-6 describe the DCC Counter1 Seed register.
Figure 15-11. DCC Counter1 Seed Register (DCCCNT1SEED) [offset = 10h]
31 20 19 16
Reserved COUNT1 SEED
R-0 R/WP-0
15 0
COUNT1 SEED
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 15-6. DCC Counter1 Seed Register (DCCCNT0SEED) Field Descriptions
Bit Field Value Description
31-20 Reserved 0 Read returns 0. Writes have no effect.
19-0 COUNT1 SEED Seed value for DCC Counter1.
Read in any operating mode returns the current value of seed for Counter1.
Writing in privileged mode only sets the current seed value for Counter1. Writes in user
mode are ignored.
NOTE: Seed for Counter0 must be non-zero
The DCC must only be enabled after programming a non-zero value in the COUNT1 SEED
register.
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SPNU562–May 2014 Dual-Clock Comparator (DCC) Module
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