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14.6.1 PLL Modulation Depth Measurement Control Register (SSWPLL1)
Figure 14-6 illustrates this register and Table 14-6 provides the bit descriptions. This register applies to
PLL1, but does not apply to PLL2.
Figure 14-6. SSW PLL BIST Control Register 1 (SSWPLL1) [offset = 24h]
31 16
Reserved
R-0
15 8
CAPTURE_WINDOW_INDEX
R/W-0
7 6 5 4 3 1 0
Reserved COUNTER_READ_ COUNTER_ COUNTER_EN TAP_COUNTER_DIS EXT_COUNTER_
READY RESET EN
R-0 R-0 R/W-1 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-6. SSW PLL BIST Control Register 1 (SSWPLL1) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Read returns 0. Writes have no effect.
15-8 CAPTURE_WINDOW_INDEX 0-FFh The capture counter present in the PLL wrapper will count the PLL clock edges when
the current modulation phase capture window value is equal to these bits. Should be
set equal to NR.
7 Reserved 0 Read returns 0. Writes have no effect.
6 COUNTER_READ_READY Counter read ready.
Indicates that SSW_CAPTURE_COUNT (SSWPLL2) and SSW_CLKOUT_COUNT
(SSWPLL3) can be read.
0 Counter registers in SSWPLL2 and SSWPLL3 are not ready to read.
1 Counter registers in SSWPLL2 and SSWPLL3 are ready to read.
5 COUNTER_RESET Counter reset.
If EXT_COUNTER_EN = 0, COUNTER_RESET resets SSW_CAPTURE_COUNT
(SSWPLL2) and SSW_CLKOUT_COUNT (SSWPLL3).
If EXT_COUNTER_EN = 1, this bit is ignored.
0 No impact to counters
1 If the EXT_COUNTER_EN bit is 0, then counters SSW_CAPTURE_COUNT and
SSW_CLKOUT_COUNT will be held in the reset state.
If EXT_COUNTER_EN bit is 1, then this bit will be ignored by the PLL wrapper.
4 COUNTER_EN Counter enable.
If EXT_COUNTER_EN = 0, COUNTER_EN initializes the modulation depth
measurement. (In this mode, the disable is set to occur automatically.)
If EXT_COUNTER_EN = 1, the counters are enabled/disabled with COUNTER_EN.
0 If EXT_COUNTER_EN = 0, COUNTER_EN = 0 indicates that the counters are
inactive.
If EXT_COUNTER_EN = 1, COUNTER_EN = 0 disables the counters.
1 If EXT_COUNTER_EN = 0, COUNTER_EN = 1 indicates that the counters are still
active.
If EXT_COUNTER_EN = 1, COUNTER_EN = 1 enables the counters.
516
Oscillator and PLL SPNU562–May 2014
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