Datasheet

74
RM57L843
SPNS215C –FEBRUARY 2014–REVISED JUNE 2016 www.ti.com
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System Information and Electrical Specifications Copyright © 2014–2016, Texas Instruments Incorporated
6.5.6 N2HET STC / LBIST Self-Test Coverage
Logic BIST self-test capability for N2HETs is available in this device. The STC2 can be configured to
perform self-test for both N2HETs at the same time or one at the time. The default value of the N2HET
LBIST clock prescaler is divide-by-1. However, the maximum clock rate for the N2HET STC / LBIST is
VCLK/2. N2HET STC test should not be executed concurrently with CPU STC test.
Table 6-10. N2HET Self-Test Coverage
INTERVALS TEST COVERAGE, % TEST CYCLES
0 0 0
1 70.01 1365
2 77.89 2730
3 81.73 4095
4 84.11 5460
5 86.05 6825
6 87.78 8190
7 88.96 9555
8 89.95 10920
9 90.63 12285