Datasheet
www.ti.com
PLL
14.5.2.4 Changing the PLL Operating Point While the PLL is Active
Once the valid bit (CLKSRnV bit in the Clock Source Valid Status Register (CSVSTAT) of the System and
Peripheral Control Registers) is set, software may change values to the PLL. If the change of values
results in a small percentage change to the VCO frequency (∆f
OutputCLK
< 0.1 × f
OutputCLK
), then these
changes can be done on-the-fly. In this mode, the values are updated into the PLL synchronously, and the
PLL re-locks to the new value without gating the clocks or the slip bits. If the operating point change is too
large, then the slip bits will be set.
Conversely, if the changes to the VCO frequency are large, then the PLL should be disabled prior to
changing the values. Typically, any change to the REFCLKDIV field or large changes to the PLLMUL field
in the PLL Control Register 1 (PLLCTL1) of the System and Peripheral Control Registers requires a
complete disable-and-relock strategy.
14.5.2.5 Summary of PLL Timings
In addition to controlling the lock period and disabling the clock during an ODPLL change, the PLL also
generates reset delays. When power-on reset is released (nPORRST 0 --> 1), that release is delayed by
1024 OSCIN cycles so that it is released at the same time that the oscillator valid is asserted. The system
reset release is delayed by an additional 8 oscillator clock cycles.
Table 14-3. State Machine Timings
LPOMONCTRL.16 = 0 LPOMONCTRL.16 = 1
Counters clocked by OSCIN /1 Counters clocked by OSCIN /4
nPORRST delay T
nPORRST
= 1024 x T
OSCIN
T
nPORRST
= 1024 x T
OSCIN
nRST delay T
nRST
= 1032 x T
OSCIN
T
nRST
= 1032 x T
OSCIN
OSC valid T
OSCVALID
= 1024 x T
OSCIN
T
OSCVALID
= 1024 x T
OSCIN
Lock T
Lock
= (127 x T
OSCIN
) + (1024 x NR x T
OSCIN
) T
Lock
= (127 x 4 x T
OSCIN
) + (1024 x NR x T
OSCIN
)
Enable clocks after
T
Enable
= 6 x T
OSCIN
T
Enable
= 18 x T
OSCIN
lock
Disable clocks after
T
Enable
= 150 x T
OSCIN
T
Enable
= 582 x T
OSCIN
lock
Change ODPLL T
ODPLL
= 3 x T
OSCIN
T
ODPLL
= 3 x 4 x T
OSCIN
511
SPNU562–May 2014 Oscillator and PLL
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated