Datasheet

RTIDIV
f
f
RTISRC
VCLK
´³ 3
PLL www.ti.com
14.5.2.2 PLL Disable
The clock sources (for example, OSC, PLL) are disabled by setting the appropriate bit in the Clock Source
Disable Register (CSDIS) or setting the appropriate bit in the Clock Source Disable Set Register
(CSDISSET) of the System and Peripheral Control Registers. These bit allow the clock to disable but do
not force the behavior until the clock is no longer used as the source for a clock domain (for example,
GCLK, VCLK, VCLK2, RTICLK).
The PLL receives a signal to disable after the clock is no longer used by any clock domain. Within the
PLL, the clock is disabled and the appropriate CLKSRnV bit for the PLL in the Clock Source Valid Status
Register (CSVSTAT), of the System and Peripheral Control Registers, becomes inactive. Then the PLL is
placed into a low power state after the following length of time:
LPOMONCTRL.16 = 0 LPOMONCTRL.16 = 1
Counters clocked by OSCIN /1 Counters clocked by OSCIN /4
Disable clocks after
T
Enable
= 150 × T
OSCIN
T
Enable
= 582 × T
OSCIN
lock
14.5.2.3 OD-Divider Change
The PLL gates the clock if the ODPLL bit-field is changed while the PLL is active. The output clock from
the PLL is gated for 3 or 12 OSCIN clock cycles. As the post-ODCLK is gated in the low phase, the output
clock to the device -- PLL CLK -- may be gated in a high or low phase though the transition is always
glitchless.
LPOMONCTRL.16 = 0 LPOMONCTRL.16 = 1
Counters clocked by OSCIN /1 Counters clocked by OSCIN /4
Change ODPLL T
ODPLL
= 3 × T
OSCIN
T
ODPLL
= 3 × 4 × T
OSCIN
NOTE: ODPLL change should occur prior to enabling asynchronous clock domains
Since changing the ODPLL bit-field causes the PLL CLK to be gated, these changes to
ODPLL should be completed before configuring a clock domain for an asynchronous clock
source. Some clock domains (RTICLK, VCLK2) require a frequency relationship to the
VCLK.
If the PLL is clocking VCLK and it is stopped for some cycles, then the frequency relationship
is temporarily violated.
Many asynchronous domains require frequency relationships between VCLK and the
asynchronous domain. Therefore, if the PLL clock is the source for GCLK, HCLK, and VCLK,
then the gating produces a short-term change in the PLL clock frequency (and hence also
the VCLK frequency). As such, this frequency change could violate the requirements for an
asynchronous clock domain.
510
Oscillator and PLL SPNU562–May 2014
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