Datasheet

RTIDIV
f
f
RTISRC
VCLK
´³ 3
1]0...2[ += ODPLLOD
1]0...8[ += SPRRATENS
20 4 8
)1]0...8[_( +
=
A M O U N TS P R
N V
256
)81]0...8[]0...15[( <<++
=
MULMODPLLMUL
NF
256
)81]0...15[( <<+
=
PLLMUL
NF
1]0...5[ += REFCLKDIVNR
www.ti.com PLL
Table 14-2. PLL Value Encoding
PLL
NR
(4)
Non-modulated:
(5)
Modulated:
NF
(6)
NV
(7)
NS
(8)
OD
(9)
NOTE: ODPLL change should occur prior to enabling asynchronous clock domains
Since changing the ODPLL bit-field causes the PLL CLK to be gated, these changes to
ODPLL should be completed before configuring a clock domain for an asynchronous clock
source. Some clock domains (RTICLK, VCLK2) require a frequency relationship to the
VCLK.
If the PLL is clocking VCLK and it is stopped for some cycles, then the frequency relationship
is temporarily violated.
Many asynchronous domains require frequency relationships between VCLK and the
asynchronous domain. Therefore, if the PLL clock is the source for GCLK, HCLK, and VCLK,
then the gating produces a short-term change in the PLL clock frequency (and hence also
the VCLK frequency). As such, this frequency change could violate the requirements for an
asynchronous clock domain.
507
SPNU562–May 2014 Oscillator and PLL
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