Datasheet

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RM57L843
SPNS215C –FEBRUARY 2014–REVISED JUNE 2016 www.ti.com
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System Information and Electrical Specifications Copyright © 2014–2016, Texas Instruments Incorporated
6.5.5 CPU Self-Test
The CPU STC (Self-Test Controller) is used to test the two Cortex-R5F CPU Cores using the
Deterministic Logic BIST Controller as the test engine.
The main features of the self-test controller are:
• Ability to divide the complete test run into independent test intervals
• Capable of running the complete test as well as running few intervals at a time
• Ability to continue from the last executed interval (test set) as well as ability to restart from the
beginning (First test set)
• Complete isolation of the self-tested CPU core from rest of the system during the self-test run
• Ability to capture the Failure interval number
• Time-out counter for the CPU self-test run as a fail-safe feature
6.5.5.1 Application Sequence for CPU Self-Test
1. Configure clock domain frequencies.
2. Select number of test intervals to be run.
3. Configure the time-out period for the self-test run.
4. Enable self-test.
5. Wait for CPU reset.
6. In the reset handler, read CPU self-test status to identify any failures.
7. Retrieve CPU state if required.
For more information see the device technical reference manual.
6.5.5.2 CPU Self-Test Clock Configuration
The maximum clock rate for the self-test is 110 MHz. The STCCLK is divided down from the CPU clock.
This divider is configured by the STCCLKDIV register at address 0xFFFFE644.
For more information see the device-specific Technical Reference Manual.
6.5.5.3 CPU Self-Test Coverage
The self-test, if enabled, is automatically applied to the entire processor group. Self-test will only start
when nCLKSTOPPEDm is asserted which indicates the CPU cores and the ACP interface are in
quiescent state. While the processor group is in self-test, other masters can still function normally
including accesses to the system memory such as the L2 SRAM. Because uSCU is part of the processor
group under self-test, the cache coherency checking will be bypassed.
When the self-test is completed, reset is asserted to all logic subjected to self-test. After self-test is
complete, software must invalidate the cache accordingly.
The default value of the CPU LBIST clock prescaler is’ divide-by-1’. A prescalar in the STC module can be
used to configure the CPU LBIST frequency with respect to the CPU GCLK frequency.
Table 6-9 lists the CPU test coverage achieved for each self-test interval. It also lists the cumulative test
cycles. The test time can be calculated by multiplying the number of test cycles with the STC clock period.