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13.2.4 Power Domain Inactivity Monitor
The Power Domain Inactivity Monitor is very similar to the Checker CPU Inactivity Monitor in concept.
When a power domain is turned off, its outputs are isolated from the rest of the system. The outputs are
clamped to inactive safe values. Depending on the signals, the clamp value of a signal may be 0 or 1.
Some bus masters may be residing in the turned off power domains. Key bus signals from the power
domains which would have indicated that the bus master is generating a valid bus transaction are
compared against their clamped values.
The Power Domain Inactivity Monitor Diagnostic can also run in one of the following four operating modes:
1. Active compare
2. Self-test
3. Error forcing
4. Self-test error forcing
The operating mode can be selected by writing a dedicated key to the key register (MKEY4).
13.2.4.1 Active Compare Mode
This is the default mode on start-up.
In this mode, several critical bus signals such as the bus request control signals from the power domains
which would have indicated a valid bus transaction onto the interconnect are compared against their
clamped safe values. If a power domain is turned off, the outputs of the power domain are expected to
clamp to the inactive states. A difference between the power domain compare bus outputs and their
respective inactive states is indicated by signaling an error to the ESM which sets the error flag "CCM-
R5F - Power Domain Monitor Failure". In addition, the corresponding bus masters for which the compare
block detected the monitor failure are also captured in the CCMPDSTAT0 register.
Self-test mode, Error forcing mode and Self-test error forcing mode for Power Domain Inactivity Monitor
Diagnostic are the same as Checker CPU Inactivity Monitor Diagnostic. See Section 13.2.3.2,
Section 13.2.3.3, and Section 13.2.3.4 for details.
13.2.5 Operation During CPU Debug Mode
Certain debug operations place the CPU in a halting debug state where the code execution is halted.
Because halting debug events are asynchronous, there is a possibility for the debug requests to cause
loss of lockstep. CCM-R5F will disable all functional diagnostics upon detection of halting debug requests.
Core compare error will not be generated and flags will not update. A CPU reset is needed to ensure the
CPUs are again in lockstep and will also re-enable the CCM-R5F.
13.3 Control Registers
Table 13-7 lists the CCM-R5F registers. Each register begins on a 32-bit word boundary. The registers
support 32-bit, 16-bit, and 8-bit accesses. The base address for the control registers is FFFF F600h.
Table 13-7. Control Registers
Offset Acronym Register Description Section
00h CCMSR1 CCM-R5F Status Register 1 Section 13.3.1
04h CCMKEYR1 CCM-R5F Key Register 1 Section 13.3.2
08h CCMSR2 CCM-R5F Status Register 2 Section 13.3.3
0Ch CCMKEYR2 CCM-R5F Key Register 2 Section 13.3.4
10h CCMSR3 CCM-R5F Status Register 3 Section 13.3.5
14h CCMKEYR3 CCM-R5F Key Register 3 Section 13.3.6
18h CCMPOLCNTRL Polarity Control Register Section 13.3.7
1Ch CCMSR4 CCM-R5F Status Register 4 Section 13.3.8
20h CCMKEYR4 CCM-R5F Key Register 4 Section 13.3.9
24h CCMPDSTAT0 CCM-R5F Power Domain Status Register 0 Section 13.3.10
488
SPNU562–May 2014
CPU Compare Module for Cortex
TM
-R5F (CCM-R5F)
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